A Pipelined FFT Processor using Data Scaling with Reduced Memory Requirements
نویسندگان
چکیده
In this paper, a scaling method for large pipelined FFT implementations is proposed. Compared to existing block scaling methods, like implementations of Convergent Block Floating Point (CBFP), the memory requirements can be reduced while preserving the SNR. The FFT processor is implemented in a 0.35μm standard CMOS technology and is capable of calculating a 2048 complex point FFT or IFFT in 40μs with a maximum clock frequency of 50MHz.
منابع مشابه
A 2048 complex point FFT processor using a novel data scaling approach
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